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'The certification of our platforms for Samsung Foundry's 4LPP process ensures the highest level of silicon correlation and design robustness to enable chipmakers to realize best-in-class PPA and faster turnaround times.' 'Our close collaboration continues to accelerate technology advances to drive innovation in high-performance computing, AI accelerators, AR/VR and other popular application areas,' said Shankar Krishnamoorthy, GM and corporate staff for the Silicon Realization Group at Synopsys. The SAFE-QEDA program is designed to mitigate risks of new node adoption. 'Synopsys is an ideal partner to join forces on pathfinding efforts to facilitate new-node enablement as we further advance our roadmap on new technologies such as our upcoming 3nm gate-all-around process.'ДЄs the first EDA vendor to achieve full-flow certification for the 4LPP process via the SAFE-QEDA program, Synopsys is poised to accelerate a smooth adoption process for customers, minimizing risk and reducing turnaround time and costs.

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'Samsung Foundry is pleased to have worked closely with Synopsys to ensure readiness of its full EDA flow for our 4LPP process,' said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics. Synopsys is also developing a portfolio of DesignWareВ® Foundation IP and Interface IP that delivers low latency, high bandwidth and power efficiency for chips developed on the 4LPP process. 3DIC Compiler is a full exploration-to-signoff 3D solution to manage the complexity of hundreds of billions of transistors, while driving power, performance and area (PPA) per cubic mm silicon optimization. In addition, collaboration between the two companies has resulted in the availability of Synopsys 3DIC Compiler solution for the Samsung Foundry Multi-Die Integration (MDIв„ў) flow, which is proven on 4LPP technology.

The Synopsys solutions certified for Samsung Foundry's 4LPP process encompass the full digital, analog and mixed-signal implementation and signoff flow. The 4LPP process, which is available now, represents the latest implementation of Samsung Foundry's unique FinFET technology, which delivers chip density, performance and power advantages for SoCs fueling some of today's most in-demand applications, including high-performance computing, AI, and 5G infrastructure.

(Nasdaq: SNPS) today announced that its full EDA flow has been certified by Samsung Foundry for its new 4LPP (4nm Low Power Plus) process. Synopsys DesignWare IP for 4LPP process delivers low latency, maximum power efficiency and high bandwidth while minimizing integration risksД®xemplifying a commitment toward accelerating the development of power-efficient, advanced-node chips, Synopsys, Inc. Synopsys 3DIC Compiler has been validated for the Samsung Foundry Multi-Die Integration (MDI) flow, which incorporates the latest 4LPP process technology advances and provides scalability for hundreds of billions of transistors Synopsys Fusion Design Platform and Custom Design Platform are first to achieve Samsung Foundry certification on 4LPP process, part of the foundry's comprehensive technology roadmap to help chipmakers design and deliver faster, more power-efficient chips

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